1. Field of the Invention
The present invention relates to parity checking circuits for high speed mainframe computers. More particularly, the present invention relates to novel parity checking and regeneration parity circuits of partitioned data.
2. Description of the Prior Art
Parity checking circuits are well known and were included in the earliest electronic computer systems. Such circuits were employed at critical data paths throughout the computing system in order to validate the integrity of the data in the computing system.
Modern high speed mainframe computers attempt to employ parity checking circuits throughout the computing system wherever practical. Heretofore, partitioned registers have been employed in high speed mainframe computers. Such partitioning registers strip off or truncate data bits from data words or assimilate data bits to form a shortened data word and do not provide input or output parity checking of the shortened data, thus, any use of partitioned registers in critical data paths of a high speed computer have exposed the computing system to parity errors without means for checking such errors.
It would be desirable to provide simplified high speed parity checking logic for partitioned data, buffered or stored in partitioning registers throughout a high speed mainframe computing system.